22 February 2010


EU launches TRAMS project for reliable terascale memory systems

Financed by its Framework Program 7 (FP7) Future Emerging Technology fund, the European Commission (EC) has launched the three-year joint research project Terascale Reliable Adaptive Memory Systems. ‘TRAMS’ aims to investigate the impact of increasing variability and unreliability of components in future terascale memory systems and to create new design paradigms that can secure their reliable operation in future multicore processors and system-on-a-chip applications.

The TRAMS consortium includes Intel Corporation Iberia, the nanoelectronics research center IMEC of Leuven, Belgium, the University of Glasgow in Scotland, UK (through its Department of Electronic and Electrical Engineering's Device Modeling Group, led by professor of Device Modelling Asen Asenov), and the Universitat Politècnica de Catalunya (UPC) in Barcelona, Spain (through the research groups ‘Architecture and Compilers’ (ARCO) and ‘High Performance Integrated Circuits and Systems Design’ (HIPICS) in the departments of Computer Architecture and Electronics Engineering, respectively), with the latter’s professor Antonio Rubio as TRAMS’ project coordinator.

It is expected that, as a result of the continuing miniaturization of complementary metal-oxide semiconductor (CMOS) transistors and performance improvement described by Moore’s law, in the next decade a single silicon chip will be able to perform many billions of operations per second and provide many billions of bytes per second off-chip bandwidth. These terabyte-per-second computing capabilities should transform not only the throughput of large data centers and computing facilities but also the power, performance and functionality of personal computers, communication devices, computer games and other consumer electronics products.

The project targets transistors, circuits and systems near the end of the International Roadmap for Semiconductors (ITRS) and beyond. A starting point will be the ‘Late CMOS’ technologies after the 16nm technology generation, including novel multigate device architectures and novel channel and gate stack materials that are expected to reach important scaling challenges below 10nm dimensions. The project will also address ‘Beyond-CMOS’ emerging technologies such as nanowire transistors, quantum devices, carbon nanotubes, graphene, or molecular electronics, which are expected to scale below 5nm.

Both the Late CMOS and the Beyond CMOS technologies hold the promise of a significant increase in device integration density, complemented by an increase in system performance and functionality.

However, the individual nanoscale transistors in such terascale chips will be much more susceptible to: manufacturing faults (leading to an expected dramatic reduction in single device quality), an unprecedented increase in variability, a severe reduction in the signal-to-noise ratio, and severe reliability problems. Alternative circuit and system solutions therefore need to be investigated to deliver reliable systems out of variable and unreliable components and at a reasonable cost and design effort in order to keep harvesting the benefits fueled by technology scaling. TRAMS hence aims to be a bridge overcoming the nanoscale challenges to deliver reliable, energy-efficient and cost-effective memory cells for terascale processors in teraflop computing system architectures using nanotechnologies for both late CMOS and emerging devices.

In order to build reliable nanosystems, TRAMS will apply a specific variability and reliability-aware analysis and design flow as well as a hierarchical tolerance design, investigating novel solutions at both circuit and architecture levels.

With device design and simulation work being conducted at the University of Glasgow, central to the project is simulation software developed by Asenov (an authority on the variability of CMOS transistors and microchips) in an earlier £5.3m UK Engineering and Physical Sciences Research Council (EPSRC) eScience pilot project ‘NanoCMOS’. The NanoCMOS simulations use grid computing, which employs the processor power of thousands of linked computers to simulate how hundreds of thousands of transistors, each with their own individual characterstics, will function within a circuit.

In addition, Asenov and the University of Glasgow are establishing the firm Gold Standard Simulations to exploit the technology. “Tera-scale computing will transform the power, performance and functionality of personal computers, phones and other electronic devices as well as large computing facilities such as data centers,” believes Asenov.

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