9 November 2010


SEMATECH to present III-V MOSFET, FinFET and resistive RAM research at IEDM

At the 56th annual IEEE International Electron Devices Meeting (IEDM 2010) in San Francisco (6–8 December), technical papers will be presented by engineers from the Front End Processes (FEP) program of global semiconductor manufacturers’ research consortium SEMATECH of Austin, TX and Albany, NY, USA.

SEMATECH experts will report on resistive RAM (RRAM) memory technologies, advanced Fin and nanowire FETs for scaled CMOS devices, high-mobility III-V channel materials on 200mm silicon wafers in an industry standard MOSFET flow, and future ultra-low-power tunneling FET devices, highlighting breakthroughs addressing the growing need for higher-performance and low-power devices.

During the IEDM conference, SEMATECH’s FEP engineers will present research results at the following sessions:

  • Session 6, Monday, 6 December at 2 pm : ‘Self-aligned III-V MOSFETS Heterointegrated on a 200 mm Si Substrate Using an Industry Standard Process Flow’ demonstrates, for what is claimed to be the first time, that III-V devices on silicon can be processed in a silicon pilot line with controlled contamination, uniformity and yield while demonstrating good device performance.
  • Session 26, Wednesday, 8 December at 9:55 am : ‘Contact Resistance Reduction to FinFET Source/Drain Using Dielectric Dipole Mitigated Schottky Barrier Height Tuning’ shows, for the first time, a contact resistance reduction using dielectric dipole mitigated Schottky barrier height tuning on a FinFET source. The technique is very promising for emerging devices, alternative channel materials, and sub-22nm CMOSFETs, where the Schottky barrier height and resulting higher parasitic contact resistance are significant barriers for scaling.
  • Session 34, Wednesday, 8 December at 2 pm: ‘Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI’ reports on a dual-channel scheme for high-mobility CMOS FinFETs.

Also, on 5 December, SEMATECH will host invitational pre-conference workshops focusing on technical and manufacturing gaps affecting promising emerging memory technologies and III-V channels on silicon. Co-sponsored by equipment makers Tokyo Electron and Aixtron, the workshops will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.



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