14 October 2010


SEMATECH gate-stack symposium identifies post-22nm strategies

At the 7th Annual International Symposium on Advanced Gate Stack Technology (ISAGST) hosted by semiconductor industry research consortium SEMATECH of Albany, NY, USA earlier this month, more than 100 international researchers from industry and academia shared discoveries and outlined strategies for implementing advanced logic and memory process technologies for the sub-16nm node and beyond, focusing on new gate stacks.

The technologies covered were high-k/metal gate stacks for silicon (Si), silicon germanium (SiGe), III-V high-performance MOSFETs, metal/high-k/metal stacks for resistance change memory, flash memory, and phase-change memory.

Key observations included:

  • Progress is being made on Ge and III-V alternative channel material devices, although there was general acknowledgement that this area will require more effort and more resources to demonstrate manufacturable solutions;
  • Various presenters addressed the functional stack challenges for logic and memory centered on high-k metal gate for Si, SiGe as well as concerns over III-V high-performance MOSFETs;
  • Consensus was that, although there are many hurdles to overcome, vertical stacking seems the most promising pathway for continued scaling; and
  • To offset the slowdown in scaling and achieve uniformity and address reliability, newer more innovative materials and switching mechanisms of non-volatile memories need to be investigated further.

Other findings disclosed at the symposium included:

  • Keynote presenters from Intel’s Technology and Manufacturing Group as well as Macronix provided a comprehensive overview of transistor scaling options beyond the 15nm node and the challenges of non-volatile memories, including floating gate for planar and non-planar devices;
  • High-k/metal gate process issues were discussed by SONY, Toshiba, IBM and GLOBALFOUNDRIES, highlighting issues with stack scaling;
  • Andrew Kummel of the University of California, San Diego (UCSD) discussed density-functional theory (DFT) simulations suggesting practical pathways to improve the quality of high-k oxides on both Ge and III-V interfaces;
  • In the area of emerging memory development, resistance change memory is considered to be one of the most promising candidates for the next generation of memory; various materials, selector devices and architectures were showcased, and cross-bar architectures were discussed for future memory;
  • The impressive progress on spin transfer torque (STTRAM) was discussed by Grandis, Everspin and the University of Virginia; and
  • Several presentations explored new or alternative materials and architectures beyond CMOS devices for 2020, including electron spin devices, graphene, and nanowire transistors. Professor Kang Wang of University of California at Los Angeles (UCLA) reported that efficient spin injection into Ge has been realized using magnesium oxide (MgO) and is being optimized for spin transfer torque.

ISAGST is part of the SEMATECH Knowledge Series, a set of public, single-focused industry meetings designed to increase global knowledge in key areas of semiconductor R&D.

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