7 June 2012

Mentor Graphics, ST and Leti launch NanoElec IRT R&D program

ANR (the French National Research Agency) and CEA (the French Atomic and Renewable Energy Commission) have signed an agreement forming the Grenoble Institute of Technological Research (IRT): NanoElec Program.

Centered on Grenoble, the IRT partners aim to conduct R&D, and to share their research with all industrial sectors, especially small-, medium- and intermediate-sized enterprises, as well as to provide training in the necessary skills in these areas, specifically micro- and nano-electronics.

By bringing experts from manufacturers and public laboratories into close partnership, R&D activities will focus on 3D IC integration and integrated silicon photonics, in which Geneva-based chip maker STMicroelectronics (ST) and electronic design automation (EDA) software provider Mentor Graphics Corp of Wilsonville, OR, USA are the most involved.

Mentor Graphics’ expertise in computer-aided design (CAD) tools will make the technical achievements of ST and CEA’s Grenoble-based micro/nanotechnology R&D center Leti more accessible to system and applications designers, reckons CEA-Leti’s CEO Laurent Malier. “Mentor Graphics has a long history of doing world-class electronics R&D in France,” says the firm’s president Gregory K. Hinckley.

The NanoElec IRT is supported by CEA-Leti in partnership with manufacturers such as ST, Mentor Graphics, Soitec, Schneider, STEricsson, Bouygues, Presto Engineering and INEO, the Minalogic international competitive cluster, the Grenoble INP Institute of Technology teaching and research school, the Grenoble Ecole de Management school, Joseph Fourier university, INRIA (National Institute for Research in Computer Science and Control), CNRS (National Center for Scientific Research), the Laue Langevin Institute, and the ESRF (European Synchrotron Radiation Facility).

The semiconductor industry has followed a path defined by Moore’s Law for 40 years, but transistor miniaturization is no longer enough to improve performance and reduce consumption, notes Leti. The concept of equivalent scaling and other changes to maintain that rate of progress have been defined as ‘More than Moore’. Most important of these is 3D IC integration, which aims to increase performance by stacking components. This additional approach combines with miniaturization to increase performance while reducing costs and delays in accessing the market.

However, the new approach requires many major innovations in design, modeling, simulation, manufacturing and testing. The lack of validated CAD tools to define effective architectures, as well as the lack of appropriate characterization methods and tools to predict reliability, are some of the obstacles that must be overcome before being able to validate the 3D IC integration approach.

Consequently, the main objective of IRT’s 3D IC program is to validate an overall approach to 3D IC integration through a dedicated technical platform, taking into account the design, technological processes and characterization aspects.

Integrated silicon-photonics technologies should first address data transmission and IT markets, then general public applications and sensors for markets such as environment and health. Technical developments are hence driven first by information and communications technologies applications for data transmission, chip-to-chip links, and even intra-chip communication. As in other applications, silicon integration should lead to lower costs and smaller systems, says Leti.

However, there are still many technical challenges to be met before achieving photonic functions on a silicon circuit: providing CAD design tools, developing specific components such as laser sources, optical modulators, wide-bandwidth photo-detectors, passive waveguides, and wavelength multiplexers and demultiplexers. There is also a need to develop high-performance generic electronic circuit blocks to activate optical components, integrate photonic functions with electronic functions, and to implement low-cost testing and assembling techniques. The IRT’s integrated silicon photonic program aims to develop critical technologies and techniques to bring photonic components to a sufficient level of maturity for their commercialization.

“As with 3D IC integration, silicon photonics has been the subject of joint work between the CEA and ST for several years,” says Philippe Magarshack, ST’s corporate VP, Design Enablement & Services. Due to the NanoElec IRT, the key players and all the design and technology resources can combine to accelerate development and open up applications, he adds.

Tags: 3D IC Silicon photonics EDA software CAD design tools

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Visit: www.leti.fr

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