6 February 2014

European project COMPOSE3 targets proof of concept of 14nm 3D-stacked InGaAs/SiGe hybrid SRAM cell within three years

European scientists from both academia and industry have begun the new research project COMPOSE3, which is focused on an alternative approach to extend Moore’s Law. The goal is to reduce costs and improve the energy efficiency of electronic devices ranging from mobile phones to supercomputers. The project is based on the use of new materials to replace incumbent silicon, and on taking an innovative design approach where transistors are stacked vertically (3D stacking).

Coordinated by IBM Research in Zurich, Switzerland, COMPOSE3 is a scientific collaboration between industry, research organizations and small- and medium-size enterprises from six European countries: STMicroelectronics, CEA-Leti and the Centre National de la Recherche Scientifique (CNRS) in France; University of Glasgow in the UK; Tyndall National Institute at University College Cork in Ireland; DTF Technology GmbH in Germany; and Fundación IMDEA Materiales in Spain.

Moore’s Law predicted that the performance of an integrated circuit would double every 18 months, leading to a drastic reduction in the cost per digital function. First observed more than 50 years ago, this law has now come up against limits due to shrinking chip geometries. For example, a processor’s clock speed has barely increased in the past five years, with typical operating frequencies at 2–3GHz. In addition, the energy consumption of electronic devices is growing at a staggering rate, with estimates that it accounts for up to 10% of the total electrical energy generated in industrialized countries.

To address these challenges, the new project aims to develop a static random-access memory (SRAM) cell based on indium gallium arsenide (InGaAs) and silicon germanium (SiGe) rather than silicon. SRAM components are found in processors in a wide range of applications from smartphones to high-performance computers, and are usually fabricated from n-type and p-type field-effect transistors (nFETs and pFETs). In COMPOSE3, the nFET will use InGaAs, whereas the pFET will use SiGe. An SRAM cell has therefore been selected as the ideal test vehicle to demonstrate this kind of hybrid technology.

As charge carriers can move faster in InGaAs and SiGe than in silicon alone, the transistors can also be operated at a lower voltage, greatly reducing the power consumption of digital circuits. The chemical properties of InGaAs and SiGe also offer the possibility of stacking transistors vertically at the nanometer scale, opening up new avenues to increase the number of devices per unit area, while reducing the manufacturing costs for each transistor.

“This technology will provide a new paradigm shift in density scaling combined with a dramatic increase in the power efficiency of CMOS circuits,” says Dr Jean Fompeyrine, manager of the Advanced Functional Materials group at IBM Research – Zurich. “Our synergistic approach is based on replacing silicon with high-mobility channel materials such as SiGe and InGaAs," he adds. “Using these materials in a technology that delivers performance at low power, and at the same time provides a density increase at reduced costs, is a fantastic challenge that requires the collective knowledge of both industry and academia.”

The challenges associated with this approach are significant, particularly with regard to the minimization of electrically active defects in the vicinity of InGaAs and SiGe, the fabrication of transistors with low-resistance contacts, and thermal management during 3D stacking. The consortium partners each bring specific expertise to support this.

Within three years the team expects to unveil a proof of concept for fabricatinging the first 14nm 3D-stacked SRAM cell based on InGaAs and SiGe materials. The project also aims to demonstrate that the technology can be manufactured using standard processes in the microelectronics industry.

Tags: InGaAs SiGe

Visit: http://compose3.eu