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5 December 2018

Leti and Silvaco to develop gate-all-around SPICE compact models for designing circuits using nanowire and nanosheet technologies

At the IEEE’s 64th International Electron Devices Meeting (IEDM 2018) in San Francisco, CA, USA (1-5 December), micro/nanotechnology R&D center CEA-Leti of Grenoble, France and Silvaco Inc of Santa Clara, CA, USA (which provides electronic design automation and IP software tools for process and device development) have announced a three-year project to create unified SPICE compact models for the design of circuits using nanowire and nanosheet technologies.

The new predictive and physical compact model under development, Leti-NSP, builds on Leti’s 15 years of model development, including the Leti-UTSOI model for FD-SOI (fully depleted silicon-on-insulator) technology. The Leti-NSP compact model uses a novel methodology for the calculation of the surface potential, including quantum confinement. It can handle arbitrary cross-section shapes of stacked planar and vertical gate-all-around (GAA) MOSFETs (circular, square, rectangular) and provides a tool for exploring the design of nanowire and nanosheet device architectures.

The collaboration will make the new device models available to designers through SmartSpice, Silvaco’s high-performance parallel SPICE simulator for use by circuit designers. The corresponding model-parameters extraction flow will be implemented in Utmost IV, Silvaco’s database-driven environment for characterizing semiconductor devices, to ensure an accurate fit between simulated and measured device characteristics.

Accuracy of analysis at the nanometer scale is essential for co-optimization of silicon process technology and circuit performance. Besides accurate device characterization and simulation, a complete solution includes TCAD (technology computer-aided design) simulation, and 3D parasitic extraction. Silvaco says that its partnership with leading research institutions for atomistic TCAD, and its proven in-house extraction solver technology, will provide an accurate design technology co-optimization (DTCO) solution for nanometer technologies.

“Over two decades, CEA-Leti and Silvaco have collaborated on design-technology co-optimization, ranging from innovative TCAD simulation to the design of advanced nanoelectronics, and thus expanded and strengthened Silvaco’s suite of tools for designers,” says CEA-Leti’s CEO Emmanuel Sabonnadière. “This project continues that partnership, and when these physics-based compact models are made available to designers worldwide, they will be able to evaluate the potential of advanced nanowire-based CMOS technologies under development at CEA-Leti,” he adds.

“DTCO, including circuit simulation, is fundamental to the development of electronic devices, and shrinking silicon geometries are placing an even greater premium on accuracy to capture and evaluate all the new physical effects in nanometer design,” notes Eric Guichard, VP of Silvaco’s TCAD Division. “Building on past successes of Leti and Silvaco’s collaboration, this project will provide circuit designers and technologists with powerful, advanced design flows that combine CEA-Leti’s physical, predictive, and easy-to-use models with Silvaco’s high-accuracy EDA tools.”

Tags:  Leti Silvaco EDA software

Visit:  www.silvaco.com

Visit:  www.leti.fr

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