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Semiconductor Today Magazine


16 June 2006


Breakthrough CMOS on sSOI substrates

Freescale Semiconductor has demonstrated an advanced CMOS technology that utilizes strained silicon-on-insulator (SOI) substrates, a breakthrough that, according to the company, could deliver performance improvements and reduced power consumption for next generation semiconductor devices.

The company says the technology is made possible by using novel hybrid strain techniques that offer the performance of SOI with the enhanced carrier mobility of strained silicon. Transistors based on this technology exhibit performance increases greater than 30% over conventional technology, the company claims. These increases can in turn reduce active power consumption by more than 40% while maintaining performance levels.

"The need to control both active and standby power consumption while continuing to improve transistor performance is driving the industry to develop creative, non-traditional scaling techniques," said Suresh Venkatesan, Freescale's director of Austin Silicon Technology Solutions. "Freescale is breaking new ground by incorporating innovative materials, structures and processes into our transistor roadmap as evidenced by this strained SOI technology breakthrough."

The technology is being evaluated by Freescale for the 45-nm node and beyond. Initial applications may include power-sensitive and high-performance products such as advanced networking equipment and gaming consoles.

Freescale’s CMOS compatible hybrid strained SOI technology is demonstrated through an advanced method of selective biaxial-uniaxial strain hybridization. With this mixed strain approach, the nFET uniaxial strain can be amplified by the substrate, while the pFET can be enhanced beyond levels offered by conventional uniaxially strained silicon. This technology enables CMOS performance scaling to the 45-nm node and beyond.

The technology integrates strong SOI substrate-level strain with process-induced stressors, demonstrating drive performance boosts of up to 36 percent while simultaneously reducing gate leakage by 30 percent. This high performance-per-watt strained SOI technology widens the window for implementing active and standby power reduction techniques required for high-performance, power-sensitive applications.

Visit: http://www.freescale.com

Contact: jack.taylor@freescale.com