News: Suppliers
16 April 2021
SEL and Silvaco co-develop SPICE model of oxide semiconductor FETs
Semiconductor Energy Laboratory Co Ltd (SEL) of Atsugi, Japan and Silvaco Inc of Santa Clara, CA, USA (which provides electronic design automation and IP software tools for process and device development) have jointly developed a SPICE model of oxide semiconductor field-effect transistor (FETs) for use in applications including artificial intelligence (AI).
The crystalline oxide semiconductor CAAC-IGZO FET (c-axis aligned crystalline indium-gallium-zinc oxide FET) developed by SEL has extremely low off-leakage current, which enables ultra-low power consumption for integrated circuits including memory. The new device is expected to be key in helping to reduce power consumption in the coming AI era. Until now a compact model for SPICE simulation, essential for circuit design, has not been available and it has been difficult to reproduce detailed circuit characteristics through simulation.
The jointly developed compact, charge-based model extends the material characteristics and operation mode of CAAC-IGZO FET and is based on BSIM-CMG (the industry-standard model for multi-gate FinFETs). The new model can faithfully reproduce the characteristics of oxide semiconductor FET.
Advantage of the compact model are said to include:
- modeling of operation in the oxide semiconductor’s accumulation mode;
- modeling of L/W scalability and temperature dependence;
- support of multi-gate structure with Fin shape;
- modeling of threshold voltage control by bottom gate;
- modeling of interface trapped charge and sub-gap localized charge; and
- implemented in industry-standard Verilog-A language.
The new SPICE model card has been generated by Silvaco’s SPICE model extraction tool Utmost IV with the measured data from SEL and has been verified with Silvaco’s high-performance circuit simulator SmartSpice. This model will be used by partners who use SEL’s CAAC-IGZO FET technology.
“The CAAC-IGZO FET has a back gate, and the current can be controlled independently of the top gate,” says Takayuki Ikeda, general manager of SEL’s CD Division. “However, the design has been limited by the lack of a suitable model for circuit simulation. To eliminate this limitation, we partnered with Silvaco to develop a model for CAAC-IGZO FET,” he adds. “We hope that the new model will be adopted by the industry and enable wide adoption of CAAC-IGZO FET.”
SEL and Silvaco presented a paper on the compact model for CAAC-IGZO FET at the 5th IEEE Electron Devices Technology and Manufacturing Conference (EDTM2021) in Chengdu, China (8-11 April).
