5 April 2022
IRPS ‘best paper’ award for ST/CNR-IMM work on silicon carbide power devices
At the 2022 IEEE International Reliability Physics Symposium (IRPS) in Dallas, TX, USA (27-31 March), a team from STMicroelectronics and the Institute for Microelectronics and Microsystems at the National Research Council of Italy (Consiglio Nazionale delle Ricerche – Istituto per la Microelettronica e Microsistemi, CNR-IMM) in Catania, Italy, was recognized with the IRPS 2021 ‘best paper’ award for ‘Correlation between MOSFETs breakdown and 4H-SiC epitaxial defects’, which exposed newly discovered relations between certain defects and the viability of silicon carbide (SiC) power devices.
Non-functioning 4H-SiC dies
The paper points to two types of defects: short-term and long-term. Among the first, the most severe is the t = 0 type, since it’s non-functional from the start. For the first time, it is claimed, the paper exposes a direct relation between crystalline defects and failure rates in t = 0 4H-SiCs. Because of its physical characteristics, 4H-SiC offers better electron mobility than 6H-SiC (at 947cm2/Vs) but is easier to manufacture than 3C-SiC due to its atomic structure of four bilayers in a hexagonal lattice.
The team used atomic force microscopy (AFM) and cross-sections using scanning electron microscopes to look at t = 0. What they found is the presence of a crystalline precipitate at the bottom of the epitaxial layer that measures about 1.90µm in height. The authors’ drive to understand why these devices were ‘dead on arrival’ led them to look deeper and discover a new relationship between crystalline precipitates and the rate of defects. The paper from ST and CNR-IMM received the award because it explored SiC dies in a new way.
Since publication of the paper, ST has learned to optimize the epitaxial reactor chamber and the manufacturing process for its 4H-SiC devices. It can hence improve yields and, therefore, make even more cost-effective and longer-lasting devices. In turn, it expects 4H-SiC power MOSFETs to penetrate even more markets and applications and thus help to increase energy efficiency.
Stress-testing the remaining 4H-SiC dies - what high-temperature gate bias stress tests revealed
After the researchers winnowed out the t = 0 dies, they put the functioning ones in a package and stress-tested them. The first challenge was a high-temperature gate bias stress, which upped the electric field at the gate oxide, in order to monitor behavior in normal and harsh conditions. It was noticed that some of the devices already exhibited abnormal behavior at 3MV/cm. To understand why this happened, the researchers examined the problematic dies under AFM, which revealed the presence of bumps on the gate oxide measuring between 20nm and 30nm.
The finding helped to sort devices that appeared to work correctly at first but suffered from defects that were nearly impossible to spot during production. Not only did the paper explain why the devices had anomalous gate conduction but it showed the importance of high-temperature gate bias testing. The results should thus help foundries looking to monitor their SiC devices’ quality better.
What high-temperature reverse bias revealed
After the first stress tests, the dies underwent another trial: a high-temperature reverse bias. The benchmark lasted three months and served to simulate decades of normal use. It helped the authors to determine if all the devices would behave normally over their entire lifecycle. Also, while 98% of them did, the other 2% revealed abnormalities with gate currents seven times higher than normal. In a real-world application, such behavior would represent a severe malfunction. The challenge is that this ‘silent killer’ defect, while always there, would only manifest after years of normal use.
The authors first used a scanning electron microscope to understand what went wrong but could not perceive anything abnormal. As a result, they switched to transmission electron microscopy, which revealed the presence of a defect in the semiconductor under the gate’s insulator. To further understand what it was, the authors used AFM, which enabled them to discover a triangular defect with a height of 18-30nm, depending on the stress test’s duration. At this point, they understood that there was a threading dislocation from the substrate to the epitaxial layer. Consequently, they used scanning capacitance microscopy (SCM) to show the physical impact on the MOSFET device and explain its faulty electrical behavior.
It is only because the scientists used so many investigative technics that they were able to understand what happened, says ST. Put simply, the threading dislocation affects the valence band of the 4H-SiC device, effectively shrinking its bandgap. SiC’s wide bandgap is responsible for the device’s excellent electrical properties. Hence, anything responsible for shrinkage it will negatively impact the structure severely. In this instance, the valence band increased by about 0.8eV to 1eV, which is significant. Comparatively, SiC has a bandgap that varies between 2.3eV and 3.3eV, with 4H-SiC sitting at 3.23eV.