News: Optoelectronics
9 January 2025
imec reports first full wafer-scale fabrication of electrically pumped GaAs-based nano-ridge lasers on 300mm silicon
Nanoelectronics research center imec of Leuven, Belgium has demonstrated electrically driven gallium arsenide (GaAs)-based multi-quantum-well nano-ridge laser diodes fully, monolithically fabricated on 300mm silicon wafers in its CMOS pilot prototyping line. Achieving room-temperature continuous-wave lasing with threshold currents as low as 5mA and output powers exceeding 1mW, the results are said to demonstrate the potential of direct epitaxial growth of high-quality III-V materials on silicon (‘GaAs nano-ridge laser diodes fully fabricated in a 300mm CMOS pilot line’, Yannick De Koninck et al, Nature, volume 637, pages 63–69 (2025)). imec reckons that this provides a pathway to the development of cost-effective, high-performance optical devices for applications in data communications, machine learning and artificial intelligence.
The lack of highly scalable, native CMOS-integrated light sources has been a major roadblock for the widespread adoption of silicon photonics, notes imec. Hybrid or heterogeneous integration solutions ( such as flip-chip, micro-transfer printing or die-to-wafer bonding) involve complex bonding processes or the need for expensive III-V substrates which are often discarded after processing. This not only increases costs but also raises concerns about sustainability and resource efficiency. The direct epitaxial growth of high-quality III-V optical gain materials selectively on large-size silicon photonics wafers hence remains a highly sought-after objective.
The large mismatch in crystal lattice parameters and thermal expansion coefficients between III-V and silicon materials inevitably initiates the formation of crystal misfit defects, which are known to deteriorate laser performance and reliability. Selective-area growth (SAG), combined with aspect-ratio trapping (ART), significantly reduces defects in III-V materials integrated on silicon by confining misfit dislocations within narrow trenches etched in a dielectric mask.
“Over the past years, imec has pioneered nano-ridge engineering, a technique that builds on SAG and ART to grow low-defectivity III-V nano-ridges outside the trenches. This approach not only further reduces defects but also enables precise control over material dimensions and composition,” says imec’s scientific director Bernardette Kunert. “Our optimized nano-ridge structures typically feature threading dislocation densities well below 105cm-2. Now, imec exploited the III-V nano-ridge engineering concept to demonstrate the first full wafer-scale fabrication of electrically pumped GaAs-based lasers on standard 300mm silicon wafers, entirely within a CMOS pilot manufacturing line,” she adds.
Leveraging the low-defectivity GaAs nano-ridge structures, the lasers integrate InGaAs multiple quantum wells (MQWs) as the optical gain region, embedded in an in-situ doped p-i-n diode and passivated with an InGaP capping layer. Achieving room-temperature, continuous-wave operation with electrical injection is a major advancement, claims imec, overcoming challenges in current delivery and interface engineering. The devices show lasing at ~1020nm with threshold currents as low as 5mA, slope efficiencies up to 0.5W/A, and optical powers reaching 1.75mW, showcasing a scalable pathway for high-performance silicon-integrated light sources.
Picture: A 300mm silicon wafer containing thousands of GaAs devices with a close-up of multiple dies and a scanning electron micrograph of a GaAs nano-ridge array after epitaxy.
“The cost-effective integration of high-quality III-V gain materials on large-diameter silicon wafers is a key enabler for next-generation silicon photonics applications,” reckons Joris Van Campenhout, Fellow Silicon Photonics & director of the industry-affiliation R&D program on Optical I/O at imec. “These exciting nano-ridge laser results represent a significant milestone in using direct epitaxial growth for monolithic III-V integration,” he adds. “This project is part of a larger pathfinding mission at imec to advance III-V integration processes towards higher technological readiness, from flip-chip and transfer-printing hybrid techniques in the near term, over heterogeneous wafer- and die-bonding technologies and eventually direct epitaxial growth in the longer term.”
