News: Microelectronics
6 May 2025
Navitas launches first automotive ‘AEC-Plus’-qualified SiC MOSFETs in HV-T2Pak top-side-cooled package
Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA says that it has introduced a new level of reliability to meet the system lifetime requirements of the most demanding automotive and industrial applications. Navitas’ latest generation of 650V and 1200V ‘trench-assisted planar’ SiC MOSFETs, combined with an optimized, HV-T2Pak top-side-cooled package, delivers what is claimed to be the industry’s highest creepage of 6.45mm to meet IEC-compliance for applications up to 1200V.
The HV-T2Pak SiC MOSFETs are said to significantly increase system-level power density and efficiency while improving thermal management and simplifying board-level design and manufacturability. Target applications include electric vehicles (EV) on-board chargers (OBC) and DC-DC converters, data-center power supplies, residential solar inverters and energy storage systems (ESS), EV DC fast chargers, and HVAC motor drives.
AEC-Q101 is an automotive industry standard developed by the Automotive Electronics Council (AEC) to establish common part-qualification and quality-system standards. Navitas has created an industry-first benchmark ‘AEC-Plus’, indicating parts qualified above and beyond the existing AEC-Q101 and JEDEC product qualification standards. The firm says that this new benchmark showcases its understanding of system-level lifetime requirements and a commitment to enabling rigorously designed and validated products for demanding mission profiles in automotive and industrial applications.
The ‘AEC-Plus’ qualification standards extend further into rigorous multi-lot testing and qualification. Key additions to the existing AEC-Q101 requirements include:
- dynamic reverse bias (D-HTRB) and dynamic gate switching (D-HTGB) to represent stringent application mission profiles;
- over 2x longer power and temperature cycling;
- over 3x longer duration for static high-temperature, high-voltage tests (e.g. HTRB, HTGB);
- 200°C TJMAX qualification for overload operation capability.
Navitas’ HV-T2Pak top-side-cooled package, in an industry-standard compact form factor (14mm x 18.5mm), is optimized with a groove design in the package mold compound that extends the creepage to 6.45mm without reducing the size of the exposed thermal pad and ensuring optimal heat dissipation.
In addition, the exposed thermal pad has a nickel, nickel-phosphorus (NiNiP) plating, as opposed to tin (Sn) plating from existing TSC package solutions, which is critical to preserving the post-reflow surface planarity of the exposed pad and ensuring thermally efficient and reliable attachment to the thermal interface material (TIM).
Navitas says that its GeneSiC ‘trench-assisted planar SiC MOSFET technology’ offers up to 20% lower on-resistance under in-circuit operation at high temperatures compared with competition and superior switching figure-of-merits that result in the lowest power losses across a wider operating range. All GeneSiC SiC MOSFETs have what is claimed to be the highest-published 100%-tested avalanche capability, excellent short-circuit withstand energy, and tight threshold voltage distributions for easy paralleling.
The initial HV-T2Pak portfolio includes 1200V SiC MOSFETs with on-resistance ratings ranging from 18mΩ to 135mΩ and 650V SiC MOSFETs with on-resistance ratings ranging from 20mΩ to 55mΩ. Lower on-resistance (<15mΩ) SiCMOSFETs in the HV-T2Pak package will be announced later in 2025.
Navitas adds TOLL package to Gen-3 ‘Fast’ 650V SiC MOSFET range
