19 October 2020
EVG demos end-to-end process flow for collective die-to-wafer bonding
EV Group – a supplier of wafer bonding and lithography equipment for semiconductor, micro-electro-mechanical systems (MEMS) and nanotechnology applications – has demonstrated a complete process flow for collective die-to-wafer (D2W) hybrid and fusion bonding with sub-2μm placement accuracy utilizing existing EVG wafer bonding technology and processes, as well as existing bond interface materials.
Demonstrated at EVG’s Heterogeneous Integration Competence Center, this represents a milestone in accelerating the deployment of heterogeneous integration (HI) in next-generation 2.5D and 3D semiconductor packaging, the firm says.
Located at EVG’s headquarters, the Heterogeneous Integration Competence Center offers consultancy services, feasibility studies and demonstrations, process development support and pilot-production services. Serving as an open-access innovation incubator, it is designed to help customers accelerate technology development, minimize risk and develop differentiating technologies and products through HI/advanced packaging, all while guaranteeing the highest IP protection standards that are required for working on pre-release products. All process and integration aspects of both wafer-to-wafer and different D2W integration approaches are focus technologies at the center.
Leading-edge applications such as artificial intelligence (AI), autonomous driving, augmented/virtual reality (AR/VR) and 5G all require the development of high-bandwidth, high-performance and low-power-consumption devices without increasing production cost. As traditional 2D silicon scaling reaches its cost limits, the semiconductor industry is turning to heterogeneous integration – the manufacturing, assembly and packaging of multiple different components or dies with different feature sizes and materials onto a single device or package – in order to increase performance on new device generations. Collective D2W bonding is an essential HI process step that enables functional layer and known good die (KGD) transfer to support cost-efficient manufacturing of new types of 3D-ICs, chiplets, and segmented and 3D system-on-chip (SoC) devices, says EVG.
“For more than 20 years, EVG has provided process solutions and expertise to support the advancement of HI, including D2W bonding, where our technology has been successfully implemented in high-volume manufacturing applications,” says Markus Wimplinger, corporate technology development & IP director. “Our Heterogeneous Integration Competence Center, which is supported by our worldwide network of process technology teams, enhances our capabilities in this critical area by providing a foundation for customers and partners working with EVG to develop new 3D/HI solutions and products. Among these is our new collective D2W bonding approach, where we have demonstrated the ability to perform all key process steps in-house with high placement accuracy and transfer rate using our existing wafer bonding and debonding, metrology and cleaning process equipment along with select third-party systems from our development partners,” he adds. “We’d like to thank our partners for their role and support in enabling this important achievement. A special thanks goes to IRT Nanoelec and CEA-Leti, which both provided the substrates that were used in this demonstration.”
A technical paper highlighting the results of EVG’s collective D2W bonding process was presented at the Electrochemical Society (ECS) PRiME 2020 Conference (4-9 October) and can be downloaded from the ECS PRiME website at ecs.confex.com.